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Crack Cadence Tools Collection

Discussion in 'All Dev' started by Mendax47, Feb 17, 2019.

  1. Mendax47

    Mendax47 Registered User

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    If Anyone Have Latest Version OF Anyone Of This Please.. Share.. It Will Be A Grate Help...

    IC 617:
    Forbidden links removed.

    MMSIM 172:
    Hidden Content:
    [HIDDEN CONTENT]
    CALIBRE 2018:
    Forbidden links removed.

    SRECTRE 17.10.124:
    Forbidden links removed.

    ASSURA 615:
    Forbidden links removed.

    CONFORMAL 161:
    Hidden Content:
    [HIDDEN CONTENT]
    EXT 17.12:
    Hidden Content:
    [HIDDEN CONTENT]
    Genus 171:
    Hidden Content:
    [HIDDEN CONTENT]
    Innovus 18.10:
    Hidden Content:
    [HIDDEN CONTENT]
    Liberate 161:
    Hidden Content:
    [HIDDEN CONTENT]
    Incisive 152:
    Hidden Content:
    [HIDDEN CONTENT]
    LCU:
    Hidden Content:
    [HIDDEN CONTENT]
    PVS 161:
    Hidden Content:
    [HIDDEN CONTENT]
    SSV 161:
    Hidden Content:
    [HIDDEN CONTENT]
    MODUS171:
    Hidden Content:
    [HIDDEN CONTENT]
    CRACK:
    Hidden Content:
    [HIDDEN CONTENT]
    All of this are for Linux x64...


    ALL THE GOOGLE DRIVE LIKE IS MINE (UPLOADED BY ME) AND THE OTHERS I COLLECTED FROM MANY OTHER FORUMS.. I AM SO SORRY I COULDN'T UPLOAD THEM IN GOOGLE DRIVE BECAUSE OF MY SUPER SLOW INTERNET CONNECTION....

    HAVE A GRATE DAY
     
    Last edited by a moderator: Sep 15, 2019 at 20:34
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  2. WhiteDeath

    WhiteDeath Registered User

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    IC617 IC06.17.700 Full Setup Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Hotfix IC06.17.823, Version: IC6.1.7.500.2301 Last Update:
    Hidden Content:
    [HIDDEN CONTENT]
     
    Last edited by a moderator: Aug 27, 2019
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  3. WhiteDeath

    WhiteDeath Registered User

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    IC618 IC06.18.000 Full Setup Only:
    Hidden Content:
    [HIDDEN CONTENT]
     
    Last edited by a moderator: Aug 27, 2019
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  4. WhiteDeath

    WhiteDeath Registered User

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    SRECTRE 17.10.627 Hotfix:
    Hidden Content:
    [HIDDEN CONTENT]
    Code:
    Fixed CCRs in SPECTRE 17.1 ISR15
    -RELXPERT Merge the fix of CCR 2047605 into the SPECTRE17.1ISR release
    -SPECTRE Assert option checklimit_skip_insts is not working for APS/AMS in the SPECTRE17.1ISR3 release
    -SPECTRE  Monte Carlo analysis continues to run even after FATAL error occurs
    -SPECTRE  Performance issue occurs while simulating vsource with bit pattern in analogLib
    -SPECTRE  Spectre generates incorrect results with DC sweep on a port current on bsource while APS shows correct results
    -SPECTRE  DC sweep simulation takes a long time to complete; need to set both options useprevic=ns and supersweep=1
    -SPECTRE  Escaped <> characters in parameter name do not work in nonlinear expression in Spectre
    -SPECTRE  VVO crashes when goal is not specified under targets in the stats section
    -SPECTRE  Testcase does not converge in APS with noise
    - SPECTRE  Spectre APS shows different results from Spectre due to bsim4 device optimization
    -SPECTRE  GF22 FDX dc convergence problem
    -SPECTRE  DC op parameters are missing in Hisim2.91 model in the SPECTRE17.1 release
    -SPECTRE  Simulation error occurs with a Verilog-A module
    -SPECTRE  Cannot get alter results with -outname option
    -SPECTRE  Maskdev option does not work for subcircuits without specifying the hierarchy for reliability simulation
    -SPECTRE  Stress mode in native reliability analysis does not work in APS but runs fine with Spectre
    -SPECTRE  dyn_floatdcpath checks out incorrect floating gates with devices GF22 LDMOS
    -SPECTRE  Extrapolation method E for the upper end of table model in Verilog-A causes Spectre to abort
    -SPECTRE  Misuse of parameter in independent variable field of table model causes Spectre to crash
    - SPECTRERF Pnoise simulation produces different results across different versions of Spectre
    -SPECTRERF HBNOISE simulation produces different results in MMSIM15.1 vs SPECTRE17.1 (and SPECTRE18.1)
    -SPECTRERF PSS dc fails to converge in SPECTRE17.1 and SPECTRE18.1 but converges in older MMSIM15.1 versions
    -XPS Ignore third-party simulator option
     
    Last edited by a moderator: Aug 27, 2019
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  5. WhiteDeath

    WhiteDeath Registered User

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    HotFix IC06.18.050, Version: IC6.1.8.500.0500:
    Hidden Content:
    [HIDDEN CONTENT]
    Code:
    CCRs Fixed in IC6.1.8 and/or ICADVM18.1 ISR5 July 2019:
    CCR
    Number  TITLE  
    2126075    In ICADVM18.1 ISR4, Navigator fails to refresh after figGroup edit-in-place in Layout XL
    2124333    Multiple SimVision sessions with ADE Assembler, when killed individually, terminate also the others
    2118314    Changing design for test in maestro view deletes setup information
    2118284    Setting Stop View List to more than one view creates wrong netlist
    2117665    auCdl explicit netlist is missing the modelName on the instance line
    2117474    Labels on pins, inside a group, cannot be moved/copied to another cellview
    2117410    Changing design in ADE XL test resets analysis and outputs
    2114360    Starting create wire from an existing wire does not display the EOL halo
    2112499    ICADVM18.1 aucdl export missing device name in generated cdl file which causes LVS to fail
    2111979    Virtuoso exits abruptly when running Shift Color command on a via which is not colorable
    2110933    compileroptions are ignored in cdsTextTo5x
    2110921    Code fixes needed to support identical guard ring when empty cells exist in Modgen
    2110763    Batch checker does not check for 2d spacing table rules
    2110124    Schematic review causes *WARNING* (DB-220065)
    2110114    Check&Save procedure takes much time
    2109407    For a new view in ADE Assembler, job policy not set to the value defined by adexl.icrpStartup and defaultJobPolicy
    2109295    leHiAssignNet does not pick the net name from instance pin in Layout EXL
    2106815    AutoVia is not placing via for overlapping parallel wires with existing via
    2106782    Tree router becomes unresponsive when routing a single net in customer testcase
    2106236    For Multiple Runs option should not appear in the Job Policy Setup form in ADE Explorer
    2105423    How to set up the default job policy in ADE Explorer?
    2104512    Test settings, such as analyses and design variables are not saved when changing the design of the test
    2104039    Virtuoso exits abruptly when opening a design with display resolution set to Very High
    2103181    Wire editing commands should ignore wireType constraints when Constraint Aware editing is OFF
    2103102    Power router does not keep large end-to-end spacing from gray blockage
    2102285    CLA(0003) warning when Virtuoso is invoked with -cdslib flag and no cds.lib exists in the working area
    2102234    AutoVia performance issue on a design
    2102223    Enhance the functionality of the leHiAssignNet() command to work in Virtuoso Layout Suite EXL tier
    2101025    Error (CC-200019): PolyCurve::offset: failed to offset curve
    2100955    Modgen Grid Patter Editor assistant appears to show stack-of-series symbols incorrectly
    2100918    In IC6.1.8, Virtuoso exits abruptly with an exit code 134
    2100699    Pin metal does not cover metals on the pin metal fully with pin full coverage option in Wire Assistant
    2099834    Clicking the default button of  the Layout Editor Options form resets Default Wire Constraint Group to foundry
    2099820    Unable to create wire after changing alternate foundry constraint group
    2098814    lcePrintTechDiagnostics flags invalid purpose fillOPC
    2097629    There is a lag time when trying to plot a signal from the Results tab in ADE Assembler
    2096313    In Monte Carlo GUI, there is a character limit for the text field under Instance selection
    2095290    MYNET2 is netlisted as trireg
    2094493    Mapping pattern created in vManager is using double quotes - ADE Verifier does not honor this
    2094159    Issue in the supply net consideration during extraction with /without bang (!) in the supply net name loaded via setup.
    2093769    Crash report is generated with an incorrect name when Virtuoso exits abruptly
    2093151    In ICADVM18.1 ISR3, shapes in figGroup cannot be selected from navigator in Layout XL
    2092864    Virtuoso exits abruptly whenever customer runs write_oa if db already exists in directory instead of overwriting it
    2092064    Virtuoso exits abruptly when running Edit in Place command using Dynamic Selection Assistant with Track Pattern Assistant
    2091552    DefOut exits abruptly on pathSeg with a (possibly) derived layer
    2091174    A multiple segment ruler becomes a single segment ruler after stretching
    2091082    DRD does not support minLargeViaArrayCutSpacing in IC6.1.7
    2090859    In the ADE Stimuli form, an input bus containing a disjoint set of signals cannot be assigned a stimulus
    2090392    SDR Source Sink Map should consider WEAK pins
    2090303    Some terminals do not connect to twigs using SDR
    2089926    leRepeatCopyMoveStretch not working in ICADVM18.1 Layout EXL
    2089822    Cannot restore Job Policy Form options
    2088914    Running AMS simulation from ADE Explorer, pops up ams_ieinfo.log of previous run for multiple scope IE-card Base Setup(OSS/UNL) tab
    2087611    Fatal error occurred when using resource estimation feature in job setup in ADE Assembler
    2087439    Make Metal3 WSPs visible in Track Pattern Assistant, zoom in and Virtuoso exits abruptly
    2087435    Since IC6.1.7 ISR23 and IC6.1.8 ISR1, unable to close multiple Return to Level forms, other than to restart Virtuoso
    2087364    Unable to run extraction due to missing supply set
    2086922    Analog port is incorrectly related to ground net instead of supply net
    2086720    Missing related supplies for digital and analog ports
    2086681    why is WLAN11AX baseband circuit power out 3dB lower than WLAN11AX passband?
    2086595    leConvertShapeToPolygon leaves behind original PathSeg/Wire
    2086320    vfoGetInstWithMissingCache command corrupts FGR instance
    2086061    Missing related supply pins for analog ports
    2084597    loading via variant using Load Physical View
    2084530    Pnoise GUI adds additional analyses when switching between Spectre 16.1 and 17.1
    2083299    Virtuoso Visualization and Analysis XL 'Fit Visible Traces' for multiple waveforms plotted in different Y-axis
    2083203    Single mouse wheel click generating multiple zoom commands.
    2082725    labels are not aligned to pin center after running Align-To-Top-Route
    2082713    textDisplay prompt from group when copying across cellviews
    2082158    How to use the maximum number of jobs with maxJobs when GroupRunA is enabled
    2081979    ADE Verifier cannot stop batch run
    2081236    DEFOUT of via stack gives Warning OALEFDEF-50107 of route segments then issues ERROR OALEFDEF-50093
    2079825    ctuTech::sort causing long delay while opening cellview when techfile has large number of derived layers
    2078610    Noise summary 'sort by hierarchy' does not work if input source is specified in noise analysis
    2077714    VHDL UNL netlister 'time' parameter has double quotes which causes problem
    2077309    The history of the opened view disappears after ADE Explorer/ADE Assembler transition when opening schematic
    2076557    IC6.1.8: verifRun does not honor pre-run script in ?impSet argument
    2075736    VPM loads lpSetup.il with wrong keyword, does not issue a warning and proceeds
    2075557    minVoltageExtension check gets missed until minDualExtension and minQuadrupleExtension is enabled
    2074885    What is the recommended SDR setting
    2074704    Close data corrupts open maestro view and has lost output settings
    2074190    Error in AMS simulation, causes another running AMS simulation to exit
    2073338    Return To Level' form cannot disappear and close
    2072999    Adjust Blocks command is not following User Units
    2072970    Pin Planner should not replace other pins when Selected Pins option is used
    2072748    Plotting Histogram with thick trace lines makes symbols/sigma notations almost invisible
    2072045    Missing marker when via is not maximized
    2069758    Need to improve the precision of Eye period in Eye Diagram Assistant
    2069337    The Property Editor field does not get updated correctly when multiple items are selected and edited
    2068954    spectrumMeasurement function with int(VAR(X)) issues error message during ADE L parametric analysis
    2068797    Text box resizing issue in Result Display Window
    2067697    Abstract Generator does not extract gate and diffusion area in some cases
    2067476    Seeing the wrong color on some shapes with metal1, LPPs e1, e2, e3
    2064282    Via cut packet covers entire via when selected for move or copy with trim shape abstraction selected
    2062598    AMS gives no error after adding pins and simulating in read mode where Spectre does
    2062557    Stretching wire creates wide connections (and errors) at internal wire connection points
    2061908    ICADV12.3 ISR23 DEFOUT is missing connections in DEF OUT section
    2058266    Virtuoso error when switching to Layout XL application
    2053988    Vsource and isource reset CDF parameters when srcType is changed
    2053675    IC6.1.8 ISR1: Faults are not created with *Error* strcat: argument #1 should be either a string or a symbol
    2049815    Virtuoso Space-based Router: Trunk generation not working
    2038760    'Display TMI self-heating/aging results' points to wrong 'input.tmideg0' file
    2035560    analogLib Library - vsource parameters cleared when changing source type
    2024486    psfxl waveform cannot be plotted when using -incsize
    2021087    DEFin is not reporting warning/error message when seeing -ve extension value in a pathSeg
    2019051    NC-Verilog netlister is not running incrementally
    2018948    Behavior when CDF Property 'paramLabelSet' line contains space characters
    2018326    ICADV12.3 ISR22: leMoveCellViewOrigin caused via to be dislocated
    1999475    ICADV12.3 ISR22: WSP checker produces inconsistent violation on boundary tracks
    1987616    lxHierCheckAgainstSource() API tries to check out physConfig view in DM when run in read-only mode
    1985688    delay function with multiple gives negative values when it should not
    1981020    lxHierCheckAgainstSource() reports warning messages for creating physConfig when run in read-only mode
    1969781    Checks&Asserts visualization for AMS simulation in ADE is not possible if a .scs file is included
    1953268    Several issue about the results of evalType=sweeps with disabled test
    1950310    Sweeping frequency of harmonic causes incorrect plot in ADE XL
    1946257    parameter setup is wiped when source type changes from pulse to dc in vsource
    1932796    analogLib vsource CDF parameter srcType callback resets source type and configuration
    1924381    Visualization and Analysis XL leaking memory with repeated corner plots
    1910930    Real Time Tuning and callback interaction
    1899186    period argument of delay function does not accept family waveform
    1855164    Spectre fails due to qrcToDfII, setting vsource instances in upper case while probe in ccvs in lower case
    1804698    Visualization and Analysis XL: Ctrl-R (Reload) produces bad signal labels in legend
    1785430    Database extis when trying to save a database (OA flow)
    1780237    Unable to copy and paste multiple family waveforms in ViVA
    1735961    reload in Visualization and Analysis XL will plot one signal's all corners' result in ADE XL
    1642851    Signals exported to VCSV all appear with the same icon (voltage/current) in the RB
    1365422    Visualization and Analysis XL reload window reloads all corners not just the corner plotted
    1116065    In Visualization and Analysis XL, File --> Reload -->Current Subwindow reloads all corners result    
    
     
    Last edited by a moderator: Aug 27, 2019
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  6. WhiteDeath

    WhiteDeath Registered User

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    SPECTRE v18.10.077 Full Setup Only:
    Hidden Content:
    [HIDDEN CONTENT]
     
    Last edited by a moderator: Aug 27, 2019
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  7. WhiteDeath

    WhiteDeath Registered User

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    Hotfix SPECTRE18.10.421:
    Hidden Content:
    [HIDDEN CONTENT]
    Code:
    Fixed CCRs in SPECTRE 18.1 ISR9
    -------------------------------
    1864670 SPECTRE     Print peak value for Boolean expressions in assert with extreme=yes
    2017541 SPECTRE     Enhance Spectre DUT statement to enable mismatch variation outside the DUT
    2032409 SPECTRE     Generate a warning message if duplicate inst is specified in tapi_pwl
    2066348 SPECTRE     Enhance Spectre to support minr for pspice models
    2071543 SPECTRE     Diode compaction is not working in XPS-MS for the given testcase
    2074380 SPECTRE     Spectre didn't save current while using +dcopt with preserve_inst=all
    2075901 SPECTRE     APS gets stuck when running PSS with subcktoppoint set to yes
    2078271 SPECTRE     Verilog-A does not perform recompilation and the simulation result is wrong with CDS_AHDL_REUSE_LIB NO
    2082671 SPECTRE     Running dcmatch analysis with Spectre results in assertion failed message, but APS runs fine
    2085918 SPECTRE     Enhance Verilog-A module to support generate construct
    2090006 SPECTRE     Enhance dyn_float_tran_stat check to support ETA for ping_start
    2094758 SPECTRE     Enhance the description of COPPRV parameter for HiSIM_HV device model
    2096640 SPECTRE     The waveform has spike when the additional actime is set because of a bug in AHDL code
    2097504 SPECTRE     id and vdsat OP parameters are not saved for PSP103 device model
    2098333 SPECTRE     Reliability maskdev option does not work with gradual aging
    2099498 SPECTRE     DC analysis after alter generates a fatal error with an extra character "c"
    2101457 SPECTRE     Convergence problem occurs in dc I-V curve due to floating point exception at low temperature in bsimcmg
    2105529 SPECTRE     Spectre native reliability analysis generates a fatal error
    2106268 SPECTRE     Spectre/APS generates an arithmetic exception error (warning) in pnoise and the output is unavailable
    2106428 SPECTRE     Current going out of voltage source is not equal to current going into diode in Spectre (KCL not followed)
    2108013 SPECTRE     SPECTRE17.1 ISR11 fails to converge on trivial circuits that were working in SPECTRE17.1 ISR8
    2109639 SPECTRE     Support current probes given in format with the spfr2iprobe option
    2109792 SPECTRE     Spectre fails to close output files when running with mdl and SKI
    2111467 SPECTRE     Coredump issue occurs in Spectre while parsing .IC syntax
    2116502 SPECTRE     spectre_safety should ignore fault sampling in LF-P step-2 simulation
    2122882 SPECTRE     ENV variable in FS_INCLUDE_FAULT_LIST does not work and shows ERROR: no fault list specified
    2078352 SPECTRERF   HB crashes when using oscic=lin
    2081847 SPECTRERF   Getting FATAL (SPECTRE-18): Segmentation fault in pss simulations
    2106641 XPS         XPS consumes all machine memory (>456G) and then stops responding
    
     
    Last edited by a moderator: Aug 27, 2019
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  8. WhiteDeath

    WhiteDeath Registered User

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    Last edited by a moderator: Aug 27, 2019
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  9. WhiteDeath

    WhiteDeath Registered User

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    CONFORMAL 191 version:19.10.100 Full Setup Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Hotfix_CONFRML19.10.200:
    Hidden Content:
    [HIDDEN CONTENT]
    Code:
    Fixed CCRs for Conformal 19.1 ISR s200:
    
    LEC:
    1237571  modeling not matching DC and INCISIVE
    1558515  'report_rule_check -hdl_category' doesn't work in tclmode
    1590915  feedthrough functionality coupled with output equivalence creating FV issues
    1600778  pin equivalence from dot lib seems to take priority, warning and reports says it otherwise
    1639527  neq from rtl2map
    1644978  support IEEE P1735 RTL Encryption
    1648419  'find_cfm' crashes in customer environment
    1697800  incorrect mapping due to the flop model
    1702193  CDL vs Verilog LEC fails for flop abstraction
    1728950  message appears to be invalid
    1732781  source code for not-mapped Z gate does not show Z gate, only takes user to module instantiation
    1805399  unresolved aggregate
    1836966  crash with full chip flatten
    1839919  HRC3.3 error for the parameters
    1849630  BBOX issue with LEC
    1855453  unresolved aggregate parsing error
    1875415  crash with 'set_rule_handling RTL19.3 -error -continue'
    1925347  18.1 code bash: ensure the help for write template gives the options that we can use for tag_name
    1933453  smart lec runtime degraded with 'set datapath option -auto'
    1982294  need feature for customer package testcase for Cadence
    2007300  CECO cutpoint flow gives errors
    2028284  how to avoid this true non-eq
    2032194  enhance add pin equivalence to support -instance option
    2035708  parse error where none is expected
    2039232  crash using VHDL 2008
    2041790  modeling stuck in 18.2
    2049762  reporting error with 'not' in vhdl port mapping
    2051018  crashes during the elaboration stage of vhdl design
    2052129  hang while using use_renaming switch
    2059085  convert a DFF to constant when it is not supposed to
    2059530  modeling of macro involving reset value x potentially causing neq
    2066492  request to add hierarchical capability to add donttouch register
    2068678  enhance 'analyze results' command to add 16 CPU prediction
    2070554  6 Not Mapped DFFs causing noneq during RTL to compile netlist comparison
    2072930  enable -snapshot_directory for auto abort analysis in Web Interface
    2074982  IEEE P1735 Encrypted VHDL file is not being read in library space while the same file is being read in design space
    2077955  rtl2fvmap results in abort (resource sharing)
    2078472  checking out license 2x the number of threads
    2080415  compiler does not work correctly when using read_library instead of read_design
    2081843  rtl2fvmap results in 25 abort modules (resource sharing & DW_mult_pipe)
    2081848  rtl2fvmap results in 21 abort modules (resource sharing) & 2 noneq Top-level
    2083354  support guide_multibit and guide_change_names in a file
    2085208  crash in elab RTL
    2088440  sv parser exits unexpectedly in 19.10-d002 or later
    2091472  error: get_attribute: Attribute libcell is not available for Net object
    2091535  enhance naming engine to better support multibit registers with name truncation
    2092192  mapping - MB not getting mapped with JSON
    2092905  regression fails due to extra 'x' introduced in the instance path name with 19.10-d015
    2093464  CECO crashes on post ECO compare
    2096395  maps incorrectly from pin_mapping_file guidance
    2097531  cannot handle port mapping but issues HRC3.3 while Genus can parse design with change_link
    2098489  option -latch_no_holding with analyze_setup command crashes before giving result
    2098945  'analyze compare' fails to find the correct datapath analysis recipe for module
    2099653  'analyze compare' during datapath analysis consumes excessive memory resulting in IT killing job
    2102309  neq in 19.10 due to unmapped blackboxes
    2103348  multibit flops incorrectly mapped by name
    2103958  multi-threaded datapath analysis ended up "hang" in compare, while single thread does not hang
    2107567  delete instance eq crashed ECO
    2110355  debug RTL7.25 error
    2110387  verilog command file does not handle Tcl variable with a special character (dot)
    
    ECO:
    1633262  constant scan pins are being modified in the ECO netlist
    1991549  post-optimization causing NEQ patch
    2026706  hier-FEF can't write out user-specified ECO module
    2057371  'write hier dofile' missing eco pins
    2090143  neq G3. apply patch Errors with versions newer than 18.20-s300
    2094860  'analyze_eco' excessive runtime
    2100482  command 'compare_eco_hier' takes 23 hours
    2100538  version 19.10-d102 produces bigger patch
    2100752  command 'analyze_eco' errors out
    
    CLP:
    1230693  unable to load CPF, macro models are being re-read
    1636510  ISO_SUPPLIES_CONFLICT
    1928997  separate violation catergory for paths with -noiso
    2009936  request for new check around 1801 -no_isolation
    2026754  neq due to the usage of connect_logic_net
    2050683  received "Error: Below modules are added black boxes after 'REAd POwer Intent' when attempting to run CPC
    2063336  requires the voltage definitions in add_power_state even in pre_sim
    2074448  PIC reports neq on set_retention where the element list has multi-bit instance naming in revised UPF
    2075638  integrated CPF written out by CLP is adding "_reg" as suffix on the native RTL names
    2076730  'read design' took much time with hybrid mode
    2078492  CPX runs at 1% completed after 14 hrs
    2080320  implicit net creation for create_supply_port
    2088968  rtl2fvmap results 2 neq (BBOX) at top-level
    2091432  enhancement request for IEEE-1801 2013 construct use_interface_cell -port_map
    2093766  unexpected SUPPLY_SET_DRV_SUPPLY_CONFLICT at repeater inserted path
    2101071  stuck at CPX in version 19.10-d102 and run_verify 1.75
    2103390  switch matching multiple strategy pass in 17.10 but flag STRATEGY_CTRL_CONN_CONFLICT_PSW in 19.1
    
     
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  10. WhiteDeath

    WhiteDeath Registered User

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    EXT19.10.000, Version: EXT19.10-p139 Full Setup:
    Hidden Content:
    [HIDDEN CONTENT]
    Hotfix_EXT19.13.000-ISR3:
    Hidden Content:
    [HIDDEN CONTENT]
    Code:
    # Fixed CCRs List in Quantus 19.13:
    CCMPR01666815  Quantus error during the Capacitance Extraction stage
    CCMPR01793541  Improve error message when the qrcToDfII executable is not present in the IC installation path
    CCMPR01853439    xDSPF extraction gives incorrect instance pin layer information
    CCMPR01881611    Broken bus net in the extracted view if cdlOutDir is not specified
    CCMPR01905463    Need Quantus to dump  crash logs to a central location using an environment variable
    CCMPR01914801    add_cap_prefix does not output prefix for ground or coupling cap CCMPR01931831    Improve error message for advanced reduction and EM mode conflict in CCL
    CCMPR01936529    Accuracy issue when diffusion has some thickness value on multi-diffusion function    
    CCMPR01951482    Quantus errors out when the number of net names hit a limit in the remove_contact layers command  
    CCMPR01958337    Need clarification on the usage of cell-level blocking and -blocking on the same device
    CCMPR01989417    Techgen to provide better message when failing due to machine problem
    CCMPR01990368    Need enhancement in R extraction for wires including 45 degree shape
    CCMPR01992270    Improve the usability of Quantus P2P effective resistance analysis GUI flow
    CCMPR01993700    Quantus utility to check for missing port PGV connections
    CCMPR01993886    Quantus FS accuracy issue when diffusion has a thickness value on multi-diffusion function  
    CCMPR01999093    Support SPICE format for the Standalone Reduction feature    
    CCMPR02007530    Support SPICE format for the Standalone Reduction feature
    CCMPR02009305    Quantus extracts a large and non-symmetric resistance for a symmetric layout
    CCMPR02012990    Add support for Smart View in Quantus for Assura LVS Input
    CCMPR02017625    Support both PGV and macro_cell (Inductor block) in top extraction
    CCMPR02019023    Accuracy issue for primitive devices (cap device)
    CCMPR02019823    1G width reported for metal resistor hiding potential EM violation
    CCMPR02026223    Gate Diffusion Fringing Cap from ICT to be distributed between gate to source/drain terminal
    CCMPR02026533    Extracted parasitic capacitance lower with higher density fill
    CCMPR02028233    Quantus Standalone Reduction accuracy issue
    CCMPR02028686    Smart View does not change the model name for customized devices
    CCMPR02029200    Quantus net cannot connect to instances in the SPEF format under some layout structures
    CCMPR02030873    Need Assura-Smart View flow support for EM/IR simulations
    CCMPR02032324    Support for selecting net name from a list or entering net name manually in Quantus Point-to-Point Resistance Calculation GUI
    CCMPR02032730    Model from .props and .spice properties should have the same behavior
    CCMPR02033066    Need Smart View support in the Assura-Quantus flow
    CCMPR02035696    Quantus versus Quantus FS cap misalignment on narrow FETs
    CCMPR02038216    Quantus run aborts when the Split Wide MOS feature is used with Cell Blocking
    CCMPR02039182    Point-to-Point Resistance analysis is grayed out in av_extracted view
    CCMPR02042233    Support Extracted View format for the Standalone Reduction feature
    CCMPR02045611    Quantus does not accept 0 for -coupling_cap_threshold_absolute
    CCMPR02045654    Support Extracted View format for the Standalone Reduction feature
    CCMPR02047597    Resistance difference with/without the "promote_instance_ports r_only" option
    CCMPR02049045    GUI for Multiple BB option
    CCMPR02049138    Quantus errors out when only critical nets are extracted using selected nets proper
    CCMPR02051920    Multi-corner extraction for the xDSPF output
    CCMPR02053635    Quantus gets internal error for PG extraction
    CCMPR02054465    Techgen simulation error
    CCMPR02056196    Cannot change pin order of LDD device
    CCMPR02057477    Symmetrical design results in significant capacitance difference
    CCMPR02059127    Quantus errors out for long lines in files of LVS database
    CCMPR02060058    Overlapped shapes in the shape server database results in 2 EM colors in 1 resistor
    CCMPR02060202    Subtype extended to be set by default for EM Analysis
    CCMPR02061740    Metal_fill -type grounded creates wrong connectivity
    CCMPR02063651    Techgen 19.10: improve warnings on layer mis-alignment
    CCMPR02065543    "maxAspectiRatio" feature required in Quantus FS
    CCMPR02066721    "maxAspectiRatio" feature required in Quantus
    CCMPR02067463    Filtering specific device in RC netlist
    CCMPR02067744    Quantus vs Quantus FS device cap correlation issue
    CCMPR02069192    Quantus GUI Update: Support needed for handling BlackBox units when netlisting for Mixed Signal simulations
    CCMPR02069522    Capacitance difference between Quantus vs Quantus FS
    CCMPR02071478    Quantus hangs when one particular cell is in parasitic_blocking_device_cells_file
    CCMPR02073070    Quantus Standalone Reduction to support SPICE format
    CCMPR02073202    Need Standalone Reduction to support SPICE netlist
    CCMPR02073317    Support SPICE format with Standalone Reduction
    CCMPR02073522    Quantus errors out in the Resistance data preparation stage
    CCMPR02074050    DOC: Add memory usage spec change from 182
    CCMPR02077866    Quantus errors out in the RC Reduction stage
    CCMPR02079098    The callProc.il file field becomes empty if the RuleSets are switched
    CCMPR02079178    Improve usability of fs_window_file
    CCMPR02087374    Incomplete EM color plot for reduced vias in the xDSPF netlist when using Quantus shape server database
    CCMPR02088314    Enhance error message for EXT UI runs with missing technology information
    CCMPR02088329    Enhance Quantus UI initial open form and scroll bar positions
    CCMPR02089030    Quantus need to improve to establish connection through PIN pin_name in the NETS/SPECIALNETS section
    CCMPR02089232    Quantus reported open net due to dropping of the 5th significant digit
    CCMPR02090536    Quantus reports inconsistent number of physical components per different CPU
    CCMPR02090596    Standalone Reduction to support Extracted View
    CCMPR02092137    Defaults button is not working
    CCMPR02092161    Extraction netlist contains hierarchical split pins delimiter syntax error in Spectre
    CCMPR02094195    Techfile accuracy issue
    CCMPR02094894    Resistance extraction failed in the macrocell blackbox flow
    CCMPR02095588    Capacitance difference between Quantus vs Quantus FS
    CCMPR02095599    Capacitance difference between Quantus vs Quantus FS
    CCMPR02097626    Error message while reading Quantus tech file step of restoreDesign in Innovus DB
    CCMPR02101030    Report DEF file name in the error message when the DEF coordinate locations are out of range
    CCMPR02101287    Description change request for "Running Quantus with Pegasus and Calibre Inputs" in EXT users manual
    CCMPR02101469    Quantus errors out at the X-DSPF netlist generation stage
    CCMPR02102274    Quantus vs. Quantus FS cap misalignment on narrow FETs
    CCMPR02104596    Improve abutment via processing for floating nets
    CCMPR02105401    Ideal net issue in the PVS flow
    CCMPR02106239    Crash is not reported to the new log file directory
    CCMPR02106348    Issue with Quantus trapezoidal shape processing
    CCMPR02106596    Resistance accuracy issue
    CCMPR02111535    Capacitance difference between Quantus vs Quantus FS
    CCMPR02113256    Quantus generated xDSPF has duplicate device instance name for two different devices
    CCMPR02117327    Missing CAP node for unrouted net
    CCMPR02112969    Handle TSV via that is connected by two LVS vias
    CCMPR02121924    Missing cap node for unrouted net
    
     
    Last edited by a moderator: Aug 27, 2019
    6 people like this.
  11. WhiteDeath

    WhiteDeath Registered User

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    GENUS19.10.000 Full Setup Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Whats New:
    https://pastebin.com/2S1gnKjc
    ------------------------------------------------------------

    INNOVUS19.10.000 Full Setup Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Whats New:
    https://pastebin.com/MmcR7X83
    ---------------------------------------------------------

    LIBERATE19.20.100 Full Setup Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Code:
    CCRs Fixed in Release 19.2 April 2019:
    
    CCR Number  TITLE                                                                                                              
    -----------------------------------------------------------------------------------------
    2076839    ECSM_rise mismatch between standalone Liberate Β vs Unified Flow
    2068878    Liberate Variety does not characterize three_state_enable/disable
    2067495    The noise validation report is empty with ccsn_char_both_formats=1
    2064378    dot variation is not characterized from LIBERATE 18.1 ISR2Β
    2060196    write_library command of Liberate errors out when writing libraries in post characterization run script on MPVT database
    2060049    Leakage power is not subtracted from hidden power when power_subtract_leakage=4 is used with MBFF
    2055969    CCSN missing for *TIE* cells
    2054717    CCSPΒ not modeled properly for tristate inverter cells
    2050838    Timing arc of internal node is missing in Header/Footer cells
    2049847    Liberate AMS GUI is incompatible with IC6.1.8
    2049679    Switch cell capacitance range in Liberate changed with switch_cell_dc_current 0 and 1
    2045332    write_socv command in Variety exits unexpectedly when generating an SOCV file
    2043767    Power values are different when using packet-arc and packet-cell modes
    2042149    Variety exits unexpectedly with packet_mode=arc after char_variation
    2040990    Liberate AMS Static Mode: Missing timing arc for pulse generator circuitΒ
    2038380    Parameter setting sim_use_init_duration=2 results in an error during sensitivity file characterization
    2038236    write_variation does not generate moment data for retain arcs
    2035614    CCSN Glitch: worst case is not captured for SPICE and .ic vs .nodeset shows different results for SPICE
    2035594    CCSN Glitch: Report is missing certain path/when conditions completely
    2034104    Liberate MX:Β define_arc attribute failed existence check in table files leading to top script table definition being used
    2033979    Cell marked failed with variation_ecsm_compatibility_mode=1
    2031073    LC LBDB-655 error showed in libraries with new CCSN format
    2030960    LBDB 667 warning with appended libs
    2030312    Significant difference between sigma numbers with ski_enable=0 vs 1 in Variety
    2030155    bus_syntax in Liberate does not update bus syntax in when/sdf condition
    2021710    CCSN glitch correlation - Liberate LV not reporting worst glitch from SPICE
    2021594    define_arc pinlist does not support bus format In Liberate
    2014281    analyze_constraint gives warning about internal node as probe and later it exits unexpectedly
    2003629    define_leafcell -type black_box -pin_position {0  1}  {vsource} results in strange supply instance in the simulation deck
    1993897    variation_nonski_char_mode=1 generates huge ocv_sigma
    1992637    interpolate_set_axis_exprs -type retain -use_worst_value does not work
    1990469    set_constraint command in Liberate MX does not expand buses
    1945976    Parse and report error/warning from VFI logs if Liberate/Spectre does not get expected results for EM from simulation
    1939334    Liberate Variety should ignore define_arc with -value on it and should model nom table when sense+nom Β is written
    1933488    Capacitance override through userdata is not working in Liberate
    1931696    write_socv causes Liberate Variety to exit unexpectedly
    1840846    set_var -type {non_seq_setup non_seq_hold} does not get applied because they map to rec/rem
    1693195    Pressing the Esc key closes the Liberate AMS GUI without saving
     
    Last edited by a moderator: Aug 27, 2019
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  12. WhiteDeath

    WhiteDeath Registered User

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    JASPERGOLD 19.06.000 Full Setup Only:
    Hidden Content:
    [HIDDEN CONTENT]
    JASPERGOLD 19.06.001 Update Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Hotfix VXE18.60.005-ISR5 Only:
    Hidden Content:
    [HIDDEN CONTENT]
    GENUS19.11.000, Version: GENUS19.11-s087 Hotfix Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Code:
    CCRs fixed in GENUS 19.11 Release Notes:
    
    --------------------------------------------------------------------------------
    001608473       Functional equivalent for legacy MBIST poweron_run,monitor and final pass/fail flags missing in PMBIST
    001655587       Enhancement request to add a command to report constraint violations in Genus
    001880249       Issue warning instead of error when UPF references libcells which are not present
    001904643       read_scandef errors when reading scandef
    001907516       One-hot pragma in Genus
    001952042       Access to interface objects not fully supported
    001967590       LEC functional mis-maps due to incorrect original_name on retimed flops for multibit mapping
    001976537       create_flow_step incorrectly has earlier -save_db in Genus 18.1x command ref along with the new write_db option
    001995634       MBIST failing timing
    002002873       Genus 19.1 errors out with "failed to load driver"
    002025379       report_constraint -check_type clock_period -all_violators results do not match Innovus results on same design
    002035897       auto_library_domain informs about TUI-726 and applies incorrect library_domain info in 19.1
    002042678       dft_trace_scandef_chains takes excessive runtime; 2 hrs for 3k chains with 100k flops
    002043839       enhance PMBIST-128 message
    002047456       Observing crash during syn_map using Genus 18.14
    002047809       update_congestion_map is having huge memory jump
    002048367       Add_pmbist should report all violations/errors together
    002049037       gsc stitching errors out in derive_opcg_logic_bits
    002049124       Crash during syn_map
    002050021       Seg Fault When Reading DB
    002050998       When will a supply set handle which is not in same scope as power domain be supported for associate_supply_set?
    002056006       MIX-driving strength MB optimization enhancement
    002056786       hang in check_power_intent -detail
    002057124       get_cell is not able to find instances with multibit_seqs_instance_naming_style auto
    002057512       Non-eq logic when blocking assignment made inside always block, EQ when continuous assignment.
    002057894       Genus is not mapping Scan flops to corresponding state-retention flops
    002060077       Can't annotate RAM output pin when SAIF file contain "\" charactor in Genus
    002061492       genus: dft lockup flop polarity
    002061698       Genus Hang during PBG GENERIC STAGE
    002065531       error during scan wrapper insertion
    002066416       stdcell placement over macro during syn_gen -phys
    002068115       Genus reports missing close brace when using define_power_model
    002068839       Generated UPF is incorrrect for power switch written out from within a macro model
    002069807       GENUS19.1_CODEBASH: multiple 19.1 version runs hang during syn_generic; no hang with v18.1
    002071393       syn_opt not fixing transition violations on Memory Pins
    002071761       write_power_intent  writes incorrect add_power_state -update for states in 2nd power model
    002073976       Wrong VDD connection with apply_power_model
    002076460       GEnus does not connect supply up correct after apply_power_model -supply_map
    002077198       Loading 18.12 DB in 19.10 causes failure in setting 'pi_no_buffering' attribute
    002077241       Duplicate definition error for port when user defined attribute is defined twice
    002078485       voltage range in add_power_state causes genus to crash
    002078629       get_clocks -quiet -filter is still returning error messages even -quiet applied
    002079432       Redundant ISO insertion by genus in case of RTL instantiated ISO cells
    002079553       QRC tech file reading fail without CFI syntax
    002079648       STRATEGY_SUPPLY_SET_CONFLICT_ISO with ISO inserted on retention pins
    002079861       Elab vs generic netlist NEQ for a mmu_intfo. EQ with 17.24 binary
    002080357       report_timing should switch to CUI mode when started in legacy and then switched to cui
    002081137       Enhancements to add cost groups to report_logic_level_histogram
    002081713       Referencing an object defined later inside a Verilog block causes VLOGPT-20
    002081765       apply_power-model -port map does not reconnect if port is tied to constant in hdl
    002081830       AON bufs inserted between boundary ports/ISO outputs even with cpi_allow_aon_buf_on_isolation 0
    002081953       syn_map -phys is not honoring preserve=true instance and converting regular buffer to AON
    002082669       puts power elements (hinst) into specific REGION if power domain name match DEF REGION name
    002084460       Scan def has invalid stop points for invalid scan flops
    002084463       Scan Def invalid for 1500 DWC flops
    002085696       Genus hangs or suspends during syn_gen (pbs_gen stage)
    002085841       read_scandef results in 1000s of error messages
    002086676       write_metric inconsistency between single-corner CUI and MMMC
    002087360       Genus 18.12 inserts 4k cpi_inv resulting in inefficient level shifter multibit conversion ratio
    002087737       apply power intent is resulting in Crash with UPF 2.1
    002087738       apply power intent is resulting in Crash with Innovus friendly UPF 2.1 (mixed mode)
    002088283       Parser for UPF 2.1 should make power state definition not dependent on brace position
    002089192       add_pmbist leaves flops with dangling inputs
    002090954       hang on rcr in read_hdl, likely caused by hdl_cdfg_early_redundancy_removal
    002090955       please port syn_opt_mt_cleanup to 19.1
    002091549       get_cells caching improvements (placeholder)
    002092201       Genus 1801 find_objects is slow - 90 minute runtime between read_power_intent & apply power intent.
    002092664       Genus deleting inserted LS cell, causing CLP violations.
    002093896       read_power_intent -1801 fails to find objects when using find_objects command.
    002093944       Apply Power Intent flagging RTLOBJ Warning on MultiArray Ports
    002094778       write_dft_rtl_module Error
    002095409       syn_gen taking 46 hours
    002095452       commit_power_intent leaves floating pins, causing NEQ issue in syn_opt netlist
    002096466       Support UPF 3.0 sytnax where   the _set was removed from many options (ex: isolation_supply_set)
    002097505       Error   : Incompatible array dimensions. [CDFG-240] [elaborate]
    002097701       Getting ERRORs when GENUS UPF is reading in INNOVUS
    002098377       is_balanced . causes CKISO cells on datapath also .
    002099693       19.1 rem_inv in iopt took 18 hrs
    002100862       Genus takes huge runtime while read/apply_power_intent UPF in Genus 19.11
    002102169       genus fails to elaborate hierarchical design
    002102407       CPI-321 warning not allowing genus to insert correct AON inv
    002102480       Crash after SYN_GEN while saving the design
    002102968       Genus -source/-sink filtering excludes valid sinks on macro
    002103198       Genus is crashing while writing out db after power intent is read
    002103618       Allow upf_version 3.1 to be specified
    002103672       Error in Write_design
    002103919       Innovus run hang after Scan Sanity Check
    002103942       "write_mmmc" command fails internally when splitting a Common UI DB
    002103956       horrible mis-correlation when using AAE on iSpatial run (placeholder)
    002107320       Customer block long pole in generic/datapath opto
    002107575       redundant level shifter cells are inserted due to map_level_shifter_cell
    002107659       report_power_intent -detail when forked ,the report table is misaligned
    002108506       Crash during dp_sharing in partiton 86
    002108743       Associate supply_set to macro  internal supply should act like apply_power_model -supply_map
    002109371       iSpatial crash during innovus transfer back to Genus
    002109573       Need namescope improvement to map packed union to UPF
    002110221       pbs_iopt erroring out do to missing argument for dft_restore_chains_cmds attribute from Genus
    002110244       iSpatial invs2genus not reading SDC
    002110331       iSpatial SEGV on CPU Design
    002110428       Genus should be able to generate the same timing, power reporting after loading the Innovus DB back during Ispatial flow
    002110736       Segmentation fault during syn_gen
    002111855       iSpatial: Extraction/Timing Different After Loading DB
    002112741       Genus fails to insert isolation cells in the design
    002114598       Missing checkpoint equation for 'blend' rewrite
    002114718       tim_endp_update consuming huge runtime during datapath opt in PBS generic stage in 19.11
    002115478       pd_pcie, rtl 2 post_commit netlist LEC failure due to no ISO insertion on constant nets
    002116029       Segmentation fault during add_pmbist
    002116140       write_design -gzip_sdc don't work correctly in 19.11
    002116942       leakage_power_effort high shows very poor power/area tradeoff compared to effort med
    002117419       iSpatial handover file to innovus uses CUI format for NDR
    002117594       stack trace from super-thread duirng syn_gen-phys CUI using 19.10-p002_1
    002118335       crash with change_link -retain_exceptions when no exceptions are present
    002118757       ISO_EN_DRV_OFF for cpi_inv inserted on isolation enable path of isolation inserted on zsrpg pins
    002118800       Non-eq with left shift expression synthesized with Genus 19.1 version but not seeing with Genus 18.1 version.
    002121567       report_logic_levels_histogram failed on post syn_opt -physical design in CUI mode
    002122244       GENUS writing out quiet hlo_identity_transform_supported_function in the output DB file
    002122960       Genus not inserting LS when add_power_state defined using triplets
    002123674       Another non-EQ with Genus 19.
    002123862       AAE timing update taking more than 10 hrs for 2m design during Genus DB import
    002124000       Genus 19.1 crashes during elab
    002124347       crash in dp with 19.11
    002124988       read_hdl errors out while reading attribute inside modport definition
    002125024       iSpatial: unable to pass database from genus to innovus during iSpatial flow
    002125218       read_db crash in 19.11-e057
    002125927       Missing equations for shift_right_mult
    002125965       Segv during commit_power_intent
    002126919       read_db crash in 19.11-e057 in N5 project
    002127014       Genus ignores the -elements option of set_retention and applies rule to entire domain thus mapping unexpected instances
    002127372       Observing NONEQs on the netlist generated from Genus 19 version which are not seen in Genus 18 version
    002128980       [elab] NEQ for RTL vs Elab in 19.1* builds
    002129222       QOR degradation in 19.11 compared to 18.14 due to large fanout of ISO cells
    002130346       No clocks in the design after coming back from INVS in iSpatial flow
    002130863       Crash during check_power_intent on Media b_ss block with 19.11-e076
    002131871       Group section missing in DEF from iSpatail run
    002133331       iSpatial: SEGV while removing the design during iSpatial
    002135609       ISO_EN_DRV_OFF errors in cypress TVIIBH8M testcase
    mod note: use HTC inside Dev sections, not HTNX!
     
    Last edited by a moderator: Aug 28, 2019
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  13. WhiteDeath

    WhiteDeath Registered User

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    STRATUS19.13.100 Update Only:
    Hidden Content:
    [HIDDEN CONTENT]
    MODUS191 Full Setup Only:
    Hidden Content:
    [HIDDEN CONTENT]
    MODUS19.11.000 Hotfix Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Code:
    Modus Version 19.11 August 2019 Release Notes:
    
     CCR#  CCR Title
    
    2052555       In Path Delay tests, some paths are getting dropped out of test
    2096734       write_vectors internal error
    2108715       extract_cellaware_defects encountered syntax errors parsing legal DSPF files
    2111446       1687 Macro Test MIPD file issue in Modus 18.12:Character limit to 'PINGROUPS' line
    2110896       Command Return Code of 0 for Failure to Obtain Modus_common_ui License
    2102449       Zero Return Code on License Failure
    2108815       MODUS 19.10 final estimated coverage is %103
    2111969       [extract_cellaware_defects] Erros out due to syntax error in DSPF which has certain expression
    2111905       [extract_cellaware_defects] Cannot parse 'PF' expression
    2111920       Unexpected Cell-aware fault model is generated due to missing pg_pins in Liberty
    2116770       Logic multi-device run does not complete simulation or print call out, memory and time but finishes with Messages
    2122064       ERROR (TBD-999) is returned when running create_logic_delay_tests in Modus ATPG version 19.10
    2122275       create_logic_tests crashes with LSF
    2125151       latsimulation issue due to UDP's in ET
    2108352       Modeinit sequence missing from 1687_HSS_OPP testmode
    2127901       No patterns being generated
    
    mod note: use HTC!
     
    Last edited by a moderator: Aug 28, 2019
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  14. WhiteDeath

    WhiteDeath Registered User

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    SPECTRE19.10.063 Full Setup Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Code:
    Fixed CCRs in SPECTRE 19.1 Base (Release Date: August 2019)
    ===========================================================
    2085878 RELXPERT    Fix the inconsistency between URI examples and documentation
    2051194 SPECTRE     Document the savefilter option
    2118285 SPECTRE     ASM-HEMT model name is wrong in Spectre Circuit Simulator Components and Device Models Reference manual in SPECTRE18.1
    2072117 SPECTRE     Enhance Verilog-A to support localparam and parameters in block declaration
    1317576 SPECTRE     Enhance the message "FATAL (CMI-2010): Assertion failed in file `dfiOut.cc' error"
    2072444 SPECTRERF   Using OSC Macro Source file causes Spectre to crash
    2085918 SPECTRE     Enhance Verilog-A module to support generate construct
    2108913 SPECTRE     Remove the obsolete 'keep_res_layer' option from the document
    2133472 SPECTRE     Add report_tapc option in the manual
    2103930 SPECTRE     Results are different (>30mv peak-to-peak) if the analyses order (AC-Tran, Tran-AC, or Tran only) changes
    
    mod note: use HTC!
     
    Last edited by a moderator: Aug 28, 2019
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  15. WhiteDeath

    WhiteDeath Registered User

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    INNOVUS19.11.000 Hotfix Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Whats New:
    https://pastebin.com/L5mzS6MT

    INCISIVE15.20.077 Hotfix Only:
    Hidden Content:
    [HIDDEN CONTENT]
    mod note: use HTC!
     
    Last edited by a moderator: Aug 28, 2019
    4 people like this.
  16. WhiteDeath

    WhiteDeath Registered User

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    Base_PVS19.10.000 Full Setup Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Code:
    PVS 19.10 Release Notes:
    #----------------------------------
    CCMPR01358521  IPVS: to correct Start DRC/LVS DE check box
    CCMPR01569697  ipvs -lvs -preset presetfile not loading schematic libName and Schematic Cellname in LVS submission form
    CCMPR01766482  PVS LVS with Not started message
    CCMPR01804780  PVS cannot be restarted if previous killed run was done during CDL netlisting (.running file not removed)
    CCMPR01975976  Need to be able to control output translator file name, i.e. db2oasis.log
    CCMPR02025524  lvs_black_box -black option is filter extra devices causing LVS MisMatch.
    CCMPR02046160  Redesign submission preferences
    CCMPR02047123  DRC RV takes too long to load a large db file
    CCMPR02067108  Add option -nocomplain to perc::properties
    CCMPR02072786  ERC RESULTS opens DRC DE instead of DRC RV after LVS run
    CCMPR02073539  #UNDEFINE commands not printed by -outrule
    CCMPR02089012  PVS DRC must set "INCR_CONN yes" for avoiding Fatal Error (SIGSEGV)
    CCMPR02091867  Density command missing violations
    CCMPR02098596  select -interact -by_net result incorrect
    CCMPR02101043  Incorrect device parameters extracted for layout netlist in hierarchical mode
    CCMPR02103434  lvs_device_type terminal mapping definition is broken the pin swap information
    CCMPR02106388  dfm fill partition gap doesn't work as correct spec
    CCMPR02107910  PVS LVS hangs in 16.14, but passes flat and hierarchical in 16.12 and earlier versions
    CCMPR02110231  LSF LVS job launch issue
    CCMPR02110329  Fix LVS Extraction Bug for AS/AD, PS/PD for MOS devices
    CCMPR02112226  Unsupported nested command when deriving layer
    CCMPR02112373  LDE parameters are not getting netlisted for all instances in *.props file in Cadence PVS
    CCMPR02112406  extent_cell command parsing failed while layout_primary and variable share the same name
    CCMPR02112603  DENSITY command aborts, most of the time
    CCMPR02112800  PVS with Pegasus licenses change
    CCMPR02115704  Behavior of max_results -drc value  is strange
    
    note:my mega.nz is fulled 50GB max out ..any recommendation for upload more stuffs will be awsome so i can share here thank you!
     
    2 people like this.
  17. WhiteDeath

    WhiteDeath Registered User

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    SSV19.11.000 Hotfix Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Whats New:
    https://pastebin.com/Svq7f6DX

    JLS19.11.000 Hotfix Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Whats New:

    Code:
    CCRs fixed in JLS19.11
    ----------------------------------------
    CCMPR02137837|clock tree tracing for icgc-latch path
    CCMPR02132509|using "-cmd" options while invoking Joules gives false message
    CCMPR02132076|Joules cannot map port of type array of interfaces from SHM
    CCMPR02123984|Error in get_cell_param when leakage power is queried for a rail
    CCMPR02109134|JLS18.13+VXE.16.1.0 PHY read error
    CCMPR02105746|read_stimulus -trace_arcs can't take arc information from trace.phy generated by classic flow
    CCMPR02122290|segmentation fault during compute_power
    CCMPR02112304|Joules power estimate post-layout
    CCMPR02106653|Joules segv while using GUI
    CCMPR02111660|Joules gui pop-up re:common_ui mode query blocks continuation of script
    CCMPR01800057|read_stimulus -resim should provide report listing reasons why ICGC EN signals weren't annotated.
    CCMPR02130998|Joules fails to annotate block input present in stimulus
    CCMPR02085425|Enhancement for replay to support dumping only levels of hierarchy instead of full pdb with -keep_in_memory option
    CCMPR01790346|plot_power_pfoile -format shm need to support multiple stimulus(PHY) for DPA-Joules flow
    CCMPR02111367|power numbers reported for rail even when the rail is off in a power mode
    CCMPR01766615|plot_power_pfoile -format {shm|fsdb} need to support multiple stimulus
    CCMPR02103062|report_power command is taking huge time to come out
    CCMPR02099412|Lower RTL annotation in 191
    CCMPR02091851|write_sdb -frame should output appropriate SDPD data
     
    Last edited: Aug 30, 2019
    2 people like this.
  18. WhiteDeath

    WhiteDeath Registered User

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    PTM19.06.001 Hotfix:
    Hidden Content:
    [HIDDEN CONTENT]
     
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  19. WhiteDeath

    WhiteDeath Registered User

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    CONFRML19.10.300 Hotfix Only:
    Hidden Content:
    [HIDDEN CONTENT]
    Code:
    =========================================
    Fixed CCRs for Conformal 19.1 ISR s300
    =========================================
    
    LEC:
    1704707  not able to resolve aborts on a completely combinational block
    1750172  go_hier status needs module results and running total
    1853597  Error: PARSE_ERROR: Parsing syntax error
    2004577  reduce unblackboxing at root module to improve runtime
    2046484  enhance usability of checkpoint
    2078446  output run_verify.tcl version in the logfile
    2088518  crashes during remodel -unfold_dff
    2099556  difference between LEC and Genus SV for ceil()
    2107452  'analyze_compare' aborts, using -flowgraph and compare is EQ
    2109150  enhancement to adding mapping method with the noneq report
    2110161  false nonequivalence in threads -compare
    2110946  crash in 19.10-p100 but passes on 18.20-p100
    2114717  nonPG-2-PG BBOX flow: CPC Error "Below modules are added black boxes after 'REAd POwer Intent'"
    2114787  crash in seq const compare
    2115320  error in d127,d128 array: dynamic array problem 1 during elaborate, but fine with 18.20-s300.n001
    2115998  internal error by add_primary_input
    2116086  memory usage goes over 200GB during elaboration
    2116850  unmapped in pin_mapping flow due to different naming in interface instantiation
    2116855  'analyze datapath -flowgraph' hangs
    2119081  why did the tool unmap this user mapping in seq const compare?
    2119670  crashes on reading mapping file
    2119815  unable to extract constraints for blackboxes from Liberty cells during Streamlined ECO Verification
    2120824  enhancement to write user-renaming rules in LEC readable format
    2125946  enhancement to have better balanced modeling
    2125957  RTL SV Parser Error RTL1.15: Mismatched types between expression and target
    2126008  RTL SV Parser Error RTL1.13: Mismatched enumeration types are in the assignment
    2128173  reports PARSE_ERROR in library file that uses "cell_footprint : tlatch ;"
    2131232  what is causing inconclusive in JSON report for Genus run
    2132790  "False" sequential constant compare NEQ
    2134216  regressive error: 19.10-s200 is NEQ; 18.20-s300.n002 is EQ
    2134892  CLP-verify crash with β€œ// Error:Total number of instances and gates 2150764039 exceeds limit” but no crash in LP-EC
    2136263  seq const compare did not map "same name" signals
    
    ECO:
    2049867  how to tell CECO there is a top level port removed? I read article "How to handle top level or blackbox ports"
    2050688  request replacement option for -delete_ecopin_dofile on analyze eco
    2075080  crash during ECO run with 'analyze_eco'
    2077043  errors out during 'analyze eco'
    2108840  command 'analyze_eco' errors out
    2116225  patch validation shows NEQ result
    2124386  NEQ patch
    2124391  streamline verification shows new NEQ points
    2126681  patch contains 4 new DLAT in quick-synth database
    2128249  Hier-FEF patch contains 1 ICG DLAT and 3 DFFs, while FEF patch doesn’t
    2128768  'analyze_eco' is failing in 19.10-p100 with "failed to find corresponding net", passes in 18.20-p100
    
    CLP:
    1536801  ISO7 debug schematics unusable - power nets displayed
    1718392  multiple strategies targeting same pin and giving error STRATEGY_CTRL_CONN_CONFLICT_PSW
    1756388  PIC: elements based no_effect violation for no_isolation elements
    1787401  power supply network schematic has no info box pop-up
    1883691  support for -local_constant in 1801 flow
    1911870  does not honor copy-and-paste commands in the GUI
    2040776  strict 1801 option not able to catch syntax issues in add_power_state
    2047528  discrepancy with 'find' command in CLP verify and LP-EC
    2051326  does not seem to flag enabled level shifter having main power mismatch violation due to location constraint
    2052632  not flagging error if there is no ISO cell with required clamp value present in the library
    2059727  splitting the reporting of STRUCT_UNDRIVEN_PIN_LP
    2097534  request not to issue CROSSING_FUNC_PATH_ISO_CLAMP_VALUE when one of the ELS is used as LS
    2105380  remove or explain ISO_MISSING_MATCHING_CELL
    2111518  considering supply ports also in find_objects for set_port_attributes command
    2114730  CPX results in NEQ
    2116381  CPX syn2pnr results in NEQ
    2120659  CPX results false NEQ on constant tie 1 net
    2120682  option to filter new extra crossing where driver has more ON than load
    2128095  enhancements to ISO_EN_CONST_MACRO and ISO_EN_INACTIVE_REDUNDANT_MACRO
    2128869  CPX results NEQ due to macro with feedthrough
    2129039  Enhancement to CPX - Tied to 1'b1 (logical netlist) vs TIEH (physical netlist) crossing
    2132583  19.10-s200 issuing critical error as it doesnt understand the supply-expr in add_power_state
    2132782  CPX on different SS from pwell
    2134174  CPX - Enhance filter "no_off_to_on_no_voltage_conflict" checking for 1801_SUPPLY_SET_WELL_FORWARD_BIAS
    2136066  1801 Linter should accept set_port_attribute -ports with ports that have "/"
    2140900  crash during 'report_rule_check -lp -verb -attr' with set_lowpower_option -enable_terminal_boundary_support
    2141365  missing "STRATEGY_SUPPLY_SET_CONFLICT_ISO" in post_synth CLP run
    
     
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  20. WhiteDeath

    WhiteDeath Registered User

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    XCELIUMMAIN19.03.013 Hotfix Only:
    Hidden Content:
    [HIDDEN CONTENT]
     
    3 people like this.